參數(shù)資料
型號(hào): DS2181AQ
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 8/32頁
文件大?。?/td> 377K
代理商: DS2181AQ
DS2181A
16 of 32
TRANSMIT MULTIFRAME BOUNDARY TIMING Figure 13
NOTES:
1. Low-high transitions on TMSYNC and/or TFSYNC must occur one TCLK period early with respect
to actual frame and multiframe boundaries. TMO follows the rising edge of TMSYNC or TFSYNC.
2. TAF transitions on true frame boundaries.
3. Delay from TSER to TPOS, TNEG is five TCLK periods.
TRANSMIT SIGNALING TIMESLOT TIMING Figure 14
RECEIVE SIGNALING
Receive signaling data is available at two outputs: RSER and RSD. RSER outputs the signaling data in
timeslot 16 at RSER. The signaling data is also extracted from timeslot 16 and presented at RSD during
the timeslots shown in Table 7. This channel-associated signaling simplifies CAS system design.
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