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參數(shù)資料
Si530/531
6
Rev. 1.1
2. Pin Descriptions
Table 9. Pinout for Si530 Series
Pin
Symbol
LVDS/LVPECL/CML Function
CMOS Function
1
OE (CMOS only)*
No connection
Output enable
0 = clock output disabled (outputs tristated)
1 = clock output enabled
2
OE
(LVPECL,LVDS,
CML)*
Output enable
0 = clock output disabled (outputs tristated)
1 = clock output enabled
No connection
3
GND
Electrical and Case Ground
4
CLK+
Oscillator Output
5
CLK–
Complementary Output
No connection
6VDD
Power Supply Voltage
*Note: OE includes a 17 k
pullup resistor to VDD.
Table 10. Pinout for Si531 Series
Pin
Symbol
LVDS/LVPECL/CML Function
1
OE (LVPECL, LVDS, CML)*
Output enable
0 = clock output disabled (outputs tristated)
1 = clock output enabled
2
No connection
3
GND
Electrical and Case Ground
4
CLK+
Oscillator Output
5
CLK–
Complementary output
6VDD
Power Supply Voltage
*Note: OE includes a 17 k
pullup resistor to VDD.
1
2
3
6
5
4
GND
NC
VDD
CLK
NC
OE
(Top View)
1
2
3
6
5
4
GND
OE
VDD
CLK+
CLK–
NC
1
2
3
6
5
4
GND
NC
VDD
CLK+
CLK–
OE
Si530
LVDS/LVPECL/CML
Si530
CMOS
Si531
LVDS/LVPECL/CML
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