參數(shù)資料
型號(hào): 514KCAXXXXXXBAGR
廠商: SILICON LABORATORIES
元件分類: XO, clock
英文描述: 250 MHz, OTHER CLOCK GENERATOR, PDSO6
封裝: 3.20 X 5 MM, ROHS COMPLIANT PACKAGE-6
文件頁(yè)數(shù): 9/32頁(yè)
文件大?。?/td> 267K
代理商: 514KCAXXXXXXBAGR
Si514
Preliminary Rev. 0.9
17
4.2. Register Detailed Description
Note:
Registers not shown are reserved. Registers with reserved bits are read-modify-write.
Register 0.
Bit
7
65
43
2
1
0
Name
LP1[3:0]
LP2[3:0]
Type
R/W
Default
Varies
Bit
Name
Function
7:4
LP1[3:0]
Sets loop compensation factor LP1. Value depends on VCO frequency.
3:0
LP2[3:0]
Sets loop compensation factor LP2. Value depends on VCO frequency.
Register 5.
Bit
7
65
43
2
1
0
Name
M_Frac[7:0]
Type
R/W
Default
Varies
Bit
Name
Function
7:0
M_Frac[7:0]
Fractional part of feedback divider M that sets up the output frequency. Frequency
updates take effect when M_Int[8:3] is written.
Register 6.
Bit
7
65
43
2
1
0
Name
M_Frac[15:8]
Type
R/W
Default
Varies
Bit
Name
Function
7:0
M_Frac[15:8] Fractional part of feedback divider M that sets up the output frequency. Frequency
updates take effect when M_Int[8:3] is written.
相關(guān)PDF資料
PDF描述
514QBCXXXXXXBAGR 125 MHz, OTHER CLOCK GENERATOR, PDSO6
514SCCXXXXXXAAG 125 MHz, OTHER CLOCK GENERATOR, PDSO6
5962-9162303MXC GRAPHICS PROCESSOR, CPGA145
5962H9215308QUX 32K X 8 STANDARD SRAM, 40 ns, DFP36
5962H9215306VMX 32K X 8 STANDARD SRAM, 60 ns, CDIP28
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