參數(shù)資料
型號(hào)： 28F640J3A
廠商： Intel Corp.
英文描述： 3 Volt Intel StrataFlash Memory(3 V 64M位英特爾StrataFlash存儲(chǔ)器)
中文描述： 3伏特英特爾StrataFlash存儲(chǔ)器（3伏6400位英特爾的StrataFlash存儲(chǔ)器）
文件頁(yè)數(shù)： 12/58頁(yè)
文件大?。?/td> 574K
代理商： 28F640J3A
28F128J3A, 28F640J3A, 28F320J3A
6
PRODUCT PREVIEW
Commands are written using standard micro-processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase, program, and lock-bit configuration. The
internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and
margining of data. Addresses and data are internally latched during program cycles.
Interface software that initiates and polls progress of block erase, program, and lock-bit
configuration can be stored in any block. This code is copied to and executed from system RAM
during flash memory updates. After successful completion, reads are again possible via the Read
Array command. Block erase suspend allows system software to suspend a block erase to read or
program data from/to any other block. Program suspend allows system software to suspend a
program to read data from any other flash memory array location.
2.1
Data Protection
Depending on the application, the system designer may choose to make the V
switchable
(available only when memory block erases, programs, or lock-bit configurations are required) or
hardwired to V
. The device accommodates either design practice and encourages optimization
of the processor-memory interface.
When V
≤
V
, memory contents cannot be altered. The CUI’s two-step block erase, byte/word
program, and lock-bit configuration command sequences provide protection from unwanted
operations even when V
is applied to V
. All program functions are disabled when V
is
below the write lockout voltage V
or when RP# is V
. The device’s block locking capability
provides additional protection from inadvertent code or data alteration by gating erase and program
operations.
3.0
BUS OPERATION
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash
memory conform to standard microprocessor bus cycles.
相關(guān)PDF資料
PDF描述
28F128 3 Volt Intel StrataFlash Memory
28F1602C3 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲(chǔ)器和靜態(tài)存儲(chǔ)器)
28F3204C3 3 V Advanced+ Stacked Chip Scale Package Memory(3V高級(jí)堆芯片封裝存儲(chǔ)器)
28F1604C3 3 Volt Advanced+ Stacked Chip Scale Package Memory(3V閃速存儲(chǔ)器和靜態(tài)存儲(chǔ)器)
28F160C18 1.8V Advanced+ Boot Block Flash Memory(1.8V高級(jí)引導(dǎo)塊閃速存儲(chǔ)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F640J3C120 制造商: 功能描述: 制造商:undefined 功能描述:
28F640J3C-120 制造商: 功能描述: 制造商:undefined 功能描述:
28F640J3D75 制造商:Intel 功能描述: 制造商: 功能描述: 制造商:undefined 功能描述:
28F640J5 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:5 Volt Intel StrataFlash? Memory
28F640L18 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:StrataFlash Wireless Memory
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